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HD74LS221
Dual Monostable Multivibrators
REJ03D0458-0300 Rev.3.00 Jul.15.2005 This multivibrator features a negative-transition-triggered input and a positive-transition-triggered input either of which can be used as an inhibit input. Pulse triggering occurs at a particular voltage level and is not directly related to the transition time of the input pulse. Schmitt-trigger input circuitry (TTL hysteresis) for B input allows jitter-free triggering from inputs with transition rates as slow as 1 V/s, providing the circuit with excellent noise immunity of typically 1.2 V. A high immunity to VCC noise of typically 1.5 V is also provided by internal latching circuitry. Once fired, the outputs are independent of further transitions of the A and B inputs and are a function of the timing components, or the output pulses can be terminated by the overriding clear. Input pulses may be of any duration relative to the output pulse. Output rise and fall times are TTL compatible and independent of pulse length. Typical triggering and clearing sequence are illustrated as a part of the switching characteristics waveforms. Pulse width stability is achieved through internal compensation and is virtually independent of VCC and temperature. In most applications, pulse stability will only be limited by the accuracy of external timing components. Jitter-free operation is maintained over the full temperature and VCC range for more than six decades of timing capacitance (10 pF to 10 F) and more than one decade of timing resistance (2 k to 100 k). Throughout these ranges, pulse width is defined by the relationship: tw (out) = Cext * Rext * 1n 2.
Features
* Ordering Information
Part Name HD74LS221P HD74LS221RPEL Package Type DILP-16 pin SOP-16 pin (JEDEC) Package Code (Previous Code) PRDP0016AE-B (DP-16FV) PRSP0016DG-A (FP-16DNV) Package Abbreviation P RP Taping Abbreviation (Quantity) -- EL (2,500 pcs/reel)
Note: Please consult the sales office for the above package availability.
Rev.3.00, Jul.15.2005, page 1 of 8
HD74LS221
Pin Arrangement
1A 1B 1CLR 1Q 2Q 2 Cext 2 Rext/Cext GND
1 2 3 4 5
Q CLR Q Q
16 15 14 13
Q CLR
VCC 1 Rext/Cext 1 Cext 1Q 2Q 2CLR 2B 2A
12 11 10 9
6 7 8
(Top view)
Function Table
Inputs Clear A L X X H X X H L H L Notes: H; high level, L; low level, X; irrelevant. ; Transition from high to low level. ; Transition from low to high level. ; one high-level pulse. ; one low-level pulse. Outputs B X X L H H Q L L L Q H H H
Block Diagram (1/2)
A Q Q
B Clear
Q Clear
Q
Rev.3.00, Jul.15.2005, page 2 of 8
HD74LS221
Absolute Maximum Ratings
Item Supply voltage Input voltage Power dissipation Storage temperature Symbol VCC VIN PT Tstg Ratings 7 7 400 -65 to +150 Unit V V mW C
Note: Voltage value, unless otherwise noted, are with respect to network ground terminal.
Recommended Operating Conditions
Item Supply voltage Output current Operating temperature Rate of rise or fall of input pulse Input pulse width Setup time External timing resistance External timing capacitance Duty cycle RT = 2 k RT = 100 k Schmitt input, B Logic Input, A A or B Clear Symbol VCC IOH IOL Topr dV/dt tw (in) tw (clear) tsu Rext Cext Min 4.75 -- -- -20 1 1 40 40 15 1.4 0 -- -- Typ 5.00 -- -- 25 -- -- -- -- -- -- -- -- -- Max 5.25 -400 8 75 -- -- -- -- -- 100 1000 50 90 Unit V A mA C V/s V/s ns ns k F
Electrical Characteristics
(Ta = -20 to +75 C)
Item Threshold voltage A B Symbol VT+ VT- VT+ VT VOH VOL IIH Input current A B, Clear IIL II Short-circuit output current Supply current Input clamp voltage Note: * VCC = 5 V, Ta = 25C IOS ICC VIK
-
Output voltage
min. -- 0.8 -- 0.8 2.7 -- -- -- -- -- -- -20 -- -- --
typ.* 1.0 1.0 1.0 0.9 -- -- -- -- -- -- -- -- 4.7 19 --
max. 2.0 -- 2.0 -- -- 0.4 0.5 20 -0.4 -0.8 0.1 -100 11 27 -1.5
Unit V V V V V V A mA mA mA mA V
Condition VCC = 4.75 V VCC = 4.75 V VCC = 4.75 V VCC = 4.75 V VCC = 4.75 V, IOH = -400 A IOL = 4 mA VCC = 4.75 V IOL = 8 mA VCC = 5.25 V, VI = 2.7 V VCC = 5.25 V, VI = 0.4 V VCC = 5.25 V, VI = 7 V VCC = 5.25 V VCC = 5.25 V Triggered VCC = 4.75 V, IIN = -18 mA Ouiescent
Rev.3.00, Jul.15.2005, page 3 of 8
HD74LS221
Switching Characteristics
(VCC = 5 V, Ta = 25C)
Item Symbol tPLH Propagation delay time tPHL tPHL tPLH Inputs A B A B Clear Clear Outputs Q Q Q Q Q Q min. -- -- -- -- -- -- 70 20 tw (out) A or B Q or Q 600 6 670 6.7 750 7.5 ms typ. 45 35 50 40 35 44 120 47 max. 70 55 80 65 55 65 150 70 ns Unit ns ns ns ns Cext = 80 pF, Rext = 2 k Cext = 0 pF, Rext = 2 k Cext = 100 pF, Rext = 10 k Cext = 1 F, Rext = 10 k CL = 15 pF, RL = 2 k Cext = 80 pF, Rext = 2 k Condition
Output pulse width
Caution in use
In order to prevent any malfunctions due to noise, connect a high frequency performance capacitor between Vcc and GND, and keep the wiring between the External components and Cext, Rext/Cext pins as short as possible.
Testing Method
Test Circuit
VCC A Input P.G. Zout = 50
A
+ Cext Cext
- Rext RL Q CL Load circuit 1
Rext /Cext
B Input P.G. Zout = 50 CLR Input P.G. Zout = 50
B
CLR
Q
Same as Load Circuit 1.
Notes:
1. CL includes probe and jig capacitance. 2. All diodes are 1S2074(H).
Rev.3.00, Jul.15.2005, page 4 of 8
HD74LS221 Waveforms 1 Trigger from B, then clear (A input is low).
tTLH 90% 1.3V 60ns 3V CLR tPLH Q tPHL Q 1.3V tPLH VOH 1.3V 1.3V VOL 1.3V 0V tPHL 3V 1.3V 0V tw (in) 90% 1.3V tTHL 3V B Input 10% 10% 0V
Note:
Input pulse: tTLH 15 ns, tTHL 6 ns, PRR = 1 MHz
Waveforms 2 Trigger from A, then clear (B input is high).
tTHL tw (in) A 90% 1.3V 90% 1.3V 0V 3V CLR 1.3V 0V tPLH Q 1.3V tPLH VOH Q tPHL 1.3V 1.3V VOL tPHL VOH 1.3V VOL tTLH 3V 10% 60ns
10%
Note:
Input pulse: tTLH 15 ns, tTHL 6 ns, PRR = 1 MHz
Rev.3.00, Jul.15.2005, page 5 of 8
HD74LS221 Waveforms 3 Trigger from B, then clear (A input is low).
tTLH B Input 10% 90% 1.3V 60ns 3V CLR 1.3V 0V VOH Q VOL 90% 10% 0V tTHL 3V
Note:
Input pulse: tTLH 15 ns, tTHL 6 ns, PRR = 1 MHz
Waveforms 4 Trigger from A (B and clear input are high).
tTHL A 90% 10% 10% tTLH 3V 90% 0V 3V Q 1.3V tw (out) tw (out) Q 1.3V 1.3V VOL 1.3V 0V VOH
Note:
Input pulse: tTLH 15 ns, tTHL 6 ns, PRR = 1 MHz
Rev.3.00, Jul.15.2005, page 6 of 8
HD74LS221 Waveforms 5 Clear overriding B, then trigger from B.
tTLH B Input
50ns 0ns 90% 90% 1.3V 1.3V 10%
tTHL 3V
1.3V 10%
0V tsu
1.3V
3V 0V
CLR
1.3V
Triggered
VOH
1.3V 1.3V
Q
Not Triggered
VOL tw (out)
Note:
Input pulse: tTLH 15 ns, tTHL 6 ns, PRR = 1 MHz
Waveforms 6 Positive transition of Clear.
tTLH B Input 10% 50ns CLR 90% 1.3V 90% 1.3V 50ns 3V 1.3V 1.3V 0V VOH Q VOL tTHL 3V 10% 0V
Note:
Input pulse: tTLH 15 ns, tTHL 6 ns, PRR = 1 MHz
Rev.3.00, Jul.15.2005, page 7 of 8
HD74LS221
Package Dimensions
JEITA Package Code P-DIP16-6.3x19.2-2.54 RENESAS Code PRDP0016AE-B Previous Code DP-16FV MASS[Typ.] 1.05g
D
16
9
1 0.89 b3
8
Z
E
A1
A
Reference Symbol
Dimension in Millimeters Min Nom 7.62 19.2 6.3 20.32 7.4 5.06 0.51 0.40 0.48 1.30 0.19 0 2.29 2.54 0.25 0.31 15 2.79 1.12 2.54 0.56 Max
e D E
L
1
A A1
e
bp
e1
b c b c
p 3
e Z ( Ni/Pd/Au plating ) L
JEITA Package Code P-SOP16-3.95x9.9-1.27
RENESAS Code PRSP0016DG-A
Previous Code FP-16DNV
MASS[Typ.] 0.15g
*1
D 9
F
16
NOTE) 1. DIMENSIONS"*1 (Nom)"AND"*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET.
bp
Index mark
*2
E
HE
c
Reference Symbol
Dimension in Millimeters Min Nom 9.90 3.95 Max 10.30
Terminal cross section ( Ni/Pd/Au plating )
1 Z e
*3
D E A2
8 bp x M L1
A1 A bp b1 c c
1
0.10
0.14
0.25 1.75
0.34
0.40
0.46
0.15
0.20
0.25
HE
0 5.80 6.10 1.27
8 6.20
A
A1
L y
e x y
0.25 0.15 0.635 0.40
1
Detail F
Z L L 0.60 1.08
1.27
Rev.3.00, Jul.15.2005, page 8 of 8
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